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IDT5T9950/A 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
INDUSTRIAL TEMPERATURE RANGE
2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCKTM II JR.
FEATURES:
* * * * * * Ref input is 3.3V tolerant 4 pairs of programmable skew outputs Low skew: 185ps same pair, 250ps all outputs Selectable positive or negative edge synchronization: Excellent for DSP applications Synchronous output enable Input frequency: - Std: 6MHz to 160MHz - A: 6MHz to 200MHz Output frequency: - Std: 6MHz to 160MHz - A: 6MHz to 200MHz 2x, 4x, 1/2, and 1/4 outputs 3-level inputs for skew and PLL range control PLL bypass for DC testing External feedback, internal loop filter 12mA balanced drive outputs Low Jitter: <100ps cycle-to-cycle Standard and A speed grades Available in TQFP package
IDT5T9950/A PRELIMINARY
DESCRIPTION:
The IDT5T9950 is a high fanout 2.5V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5T9950 has eight programmable skew outputs in four banks of 2. Skew is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. When the sOE pin is held low, all the outputs are synchronously enabled. However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are synchronously disabled. The LOCK output asserts to indicate when Phase Lock has been achieved. Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF. The IDT5T9950 has LVTTL outputs with 12mA balanced drive outputs.
*
* * * * * * * *
FUNCTIONAL BLOCK DIAGRAM
sOE
Skew Select 3 3 1F1:0 PE TEST Skew Select 3 PLL FB 3 Skew Select 3 FS 3F1:0 3 3 2F1:0
1Q0 1Q1
2Q0 2Q1
3 REF
3Q0 3Q1
Skew Select 3 3 4F1:0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
4Q0 4Q1
INDUSTRIAL TEMPERATURE RANGE
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c 2002 Integrated Device Technology, Inc.
FEBRUARY 2002
DSC 5869/3
IDT5T9950/A 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
GND REF TEST 3F0 VDD 2F1 FS 2F0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDDQ, VDD VI Description Supply Voltage to Ground DC Input Voltage REF Input Voltage Maximum Power
24 23 22 21 20 19 18 17 1F1 1F0 sOE VDDQ 1Q0 1Q1 GND GND
Max -0.5 to +4.6 -0.5 to VDD+0.5 -0.5 to +4.6 TA = 85C TA = 55C 0.7 1.1 -65 to +150
Unit V V V W C
32 3F1 4F0 4F1 PE VDDQ 4Q1 4Q0 GND 1 2 3 4 5 6 7 8 9
31
30
29
28
27
26
25
Dissipation TSTG
Storage Temperature Range
NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE(TA = +25C, f = 1MHz, VIN = 0V)
Parameter Description Input Capacitance Typ. 5 Max. 7 Unit pF CIN
10
11
12
13
14
15
16
VDDQ
VDDQ
3Q1
3Q0
2Q1
GND
TQFP TOP VIEW
PIN DESCRIPTION
Pin Name REF FB TEST (1) sOE(1) Type IN IN IN IN Description Reference Clock Input Feedback Input When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary Table) remain in effect. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H) - 2Q0 and 2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set sOE LOW for normal operation (has internal pull-down). Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock (has internal pull-up). nF[1:0] FS nQ[1:0] VDDQ VDD GND IN IN OUT PWR PWR PWR 3-level inputs for selecting 1 of 9 skew taps or frequency functions Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.) Four banks of two outputs with programmable skew Power supply for output buffers Power supply for phase locked loop, lock output, and other internal circuitry Ground
PE
IN
NOTE: 1. When TEST = MID and sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless nF[1:0] = LL.
2Q0
NOTE: 1. Capacitance applies to all inputs except TEST, FS, nF[1:0], and DS[1:0].
FB
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IDT5T9950/A 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
INDUSTRIAL TEMPERATURE RANGE
PROGRAMMABLE SKEW
Output skew with respect to the REF input is adjustable to compensate for PCB trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit (tU) which ranges from 782ps to 1.5625ns for Standard version and 6.25ps to 1.3ns for A version (see Programmable Skew Range and Resolution Table). There are nine skew configurations available for each output pair. These configurations are chosen by the nF1:0 control pins. In order to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW) are used, they are intended for but not restricted to hard-wiring. Undriven 3-level inputs default to the MID level. Where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. The Control Summary Table shows how to select specific skew taps by using the nF1:0 control pins.
EXTERNAL FEEDBACK
By providing external feedback, the IDT5T9950 gives users flexibility with regard to skew adjustment. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
FS = LOW Timing Unit Calculation (tU) VCO Frequency Range (FNOM)(1,2) Skew Adjustment Range(3) Max Adjustment: 7.8125ns 67.5 18.75% Example 1, FNOM = 25MHz Example 2, FNOM = 37.5MHz Example 3, FNOM = 50MHz Example 4, FNOM = 75MHz Example 5, FNOM = 100MHz Example 6, FNOM = 150MHz Example 7, FNOM = 200MHz tU = 1.25ns tU = 0.833ns -- -- -- -- -- 9.375ns 135 37.5% -- -- tU = 1.25ns tU = 0.833ns -- -- -- 9.375ns 270 75% -- -- -- -- tU = 1.25ns tU = 0.833ns -- 7.8125ns 67.5 18.75% tU = 1.25ns tU = 0.833ns tU = 0.625ns -- -- -- -- 7.8125ns 135 37.5% -- -- tU = 1.25ns tU = 0.833ns tU = 0.625ns -- -- 7.8125ns 270 75% -- -- -- -- tU = 1.25ns tU = 0.833ns tU = 0.625ns ns Phase Degrees % of Cycle Time 1/(32 x FNOM) 24 to 40MHz IDT5T9950 FS = MID 1/(16 x FNOM) 40 to 80MHz FS = HIGH 1/(8 x FNOM) 80 to 160MHz FS = LOW IDT5T9950A FS = MID FS = HIGH 1/(8 x FNOM) 96 to 200MHz Comments 1/(32 x FNOM) 1/(16 x FNOM) 24 to 50MHz 48 to 100MHz
NOTES: 1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. 2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for frequency multiplication by using a divided output as the FB input. 3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed -4tU in addition to whatever skew value is programmed for those outputs. `Max adjustment' range applies to output pairs 3 and 4 where 6tU skew adjustment is possible and at the lowest FNOM value.
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IDT5T9950/A 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
INDUSTRIAL TEMPERATURE RANGE
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF1:0 LL (1) LM LH ML MM MH HL HM HH Skew (Pair #1, #2) -4tU -3tU -2tU -1tU Zero Skew 1tU 2tU 3tU 4tU Skew (Pair #3) Divide by 2 -6tU -4tU -2tU Zero Skew 2tU 4tU 6tU Divide by 4 Skew (Pair #4) Divide by 2 -6tU -4tU -2tU Zero Skew 2tU 4tU 6tU Inverted(2)
NOTES: 1. LL disables outputs if TEST = MID and sOE = HIGH. 2. When pair #4 is set to HH (inverted), sOE disables pair #4 HIGH when PE = HIGH, sOE disables pair #4 LOW when PE = LOW.
RECOMMENDED OPERATING RANGE
Symbol VDD/VDDQ TA Description Power Supply Voltage Ambient Operating Temperature Min. 2.3 -40 Typ. 2.5 +25 Max. 2.7 +85 Unit V C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol VIH VIL VIHH VIMM VILL IIN Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Voltage(1) Input MID Voltage(1) Input LOW Voltage
(1)
Conditions Guaranteed Logic HIGH (REF, FB Inputs Only) Guaranteed Logic LOW (REF, FB Inputs Only) 3-Level Inputs Only 3-Level Inputs Only 3-Level Inputs Only VIN = VDD or GND VDD = Max. VIN = VDD HIGH Level MID Level LOW Level
Min. 1.7 -- VDD-0.4 VDD/2-0.2 --
Max. -- 0.7 -- VDD/2+0.2 0.4 +5 +200 +50 -- -- +100 -- 0.4
Unit V V V V V A
Input Leakage Current (REF, FB Inputs Only)
-5
--
I3 IPU IPD VOH VOL
3-Level Input DC Current (TEST, FS, nF[1:0]) Input Pull-Up Current (PE) Input Pull-Down Current (sOE) Output HIGH Voltage Output LOW Voltage
VIN = VDD/2 VIN = GND VDD = Max., VIN = GND VDD = Max., VIN = VDD VDD = Min., IOH = -12mA VDD = Min., IOL = 12mA
-50 -200 -100
-- 2 --
A A A V V
NOTE: 1. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
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IDT5T9950/A 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
5T9950 Symbol IDDQ Parameter Quiescent Power Supply Current Test Conditions(1) VDD = Max., TEST = MID, REF = LOW, PE = LOW, sOE = LOW, FS = MID All outputs unloaded IDD Power Supply Current per Input HIGH (REF and FB inputs only) FS = L IDDD Dynamic Power Supply Current per Output FS = M FS = H FS = L ITOT Total Power Supply Current FS = M FS = H FVCO = 40MHz, CL = 0pF FVCO = 50MHz, CL = 0pF FVCO = 80MHz, CL = 0pF FVCO = 100MHz, CL = 0pF FVCO = 160MHz, CL = 0pF FVCO = 200MHz, CL = 0pF
NOTES: 1. Measurements are for divide-by-1 outputs and nF[1:0] = MM. 2. For nominal voltage and temperature.
5T9950A Typ.(2) 20 Max. 30 Unit mA 30
Typ.(2) 20
Max.
VIN = 2.3V, VDD = Max., TEST = HIGH
1 190 150 130 49 -- 66 -- 103 --
30 290 230 200 -- -- -- -- -- --
1 190 150 130 -- 56 -- 80 -- 125
30 290 230 200 -- -- -- -- -- --
A
A/MHz
mA
INPUT TIMING REQUIREMENTS
5T9950 Symbol tR, tF tPWC DH FREF Description(1) Maximum input rise and fall times, 0.7V to 1.7V Input clock pulse, HIGH or LOW Input duty cycle FS = LOW Reference clock input frequency FS = MID FS = HIGH
NOTE: 1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
5T9950A Max. 10 -- 90 40 80 160 Min. -- 2 10 6 12 24 Max. 10 -- 90 50 100 200 MHz Unit ns/V ns %
Min. -- 2 10 6 10 20
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IDT5T9950/A 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
5T9950 Symbol FNOM tRPWH tRPWL tU tSKEWPR tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEW4 tDEV t() tODCV tPWH tPWL tORISE tOFALL tLOCK tCCJH tCCJM tCCJL Parameter VCO Frequency Range REF Pulse Width HIGH(1) REF Pulse Width LOW
(1)
5T9950A Max. -- -- 185 0.25 0.25 0.5 0.5 0.9 0.75 0.3 1 1.5 2 1.5 1.5 0.5 100 200 200 Min. 2 2 -- -- -- -- -- -- -- Typ. -- -- 50 0.1 0.1 0.2 0.15 0.3 -- -- -- -- -- 0.7 0.7 -- -- -- -- Max. -- -- 185 0.25 0.25 0.5 0.5 0.9 0.75 0.25 1 1.5 2 1.5 1.5 0.5 100 150 200 ps Unit ns ns ps ns ns ns ns ns ns ns ns ns ns ns ns ms
Min. 2 2 -- -- --
(5)
Typ. -- -- 50 0.1 0.1 0.2 0.15 0.3 -- -- -- -- -- 0.7 0.7 -- -- -- --
See Programmable Skew Range and Resolution Table
Programmable Skew Time Unit Zero Output Matched-Pair Skew (xQ0, xQ1)(2,3) Zero Output Skew (All Outputs)
(4)
See Control Summary Table
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)(5) Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided) Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs) Device-to-Device Skew
(2,6) (5)
-- -- -- --
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)(2) REF Input to FB Static Phase Offset(7) Output Duty Cycle Variation from 50% Output HIGH Time Deviation from 50% Output Rise Time Output Fall Time PLL Lock Time
(10) (8)
-0.3 -1
-- -- 0.15 0.15 -- -- -- --
-0.25 -1
-- -- 0.15 0.15 -- -- -- --
Output LOW Time Deviation from 50%(9)
Cycle-to-Cycle Output Jitter (peak-to-peak) (divide by 1 output frequency, FS = H) Cycle-to-Cycle Output Jitter (peak-to-peak) (divide by 1 output frequency, FS = M) Cycle-to-Cycle Output Jitter (peak-to-peak) (divide by 1 output frequency, FS = L)
NOTES: 1. Refer to Input Timing Requirements table for more detail. 2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified load. 3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. 4. tSK(0) is the skew between outputs when they are selected for 0tU. 5. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divideby-4 mode). Test condition: nF0:1=MM is set on unused outputs. 6. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.) 7. t is measured with REF input rise and fall times (from 0.7V to 1.7V) of 0.5ns. Measured from 1.25V on REF to 1.25V on FB. 8. Measured at 1.7V. 9. Measured at 0.7V. 10. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
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IDT5T9950/A 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
INDUSTRIAL TEMPERATURE RANGE
AC TEST LOADS AND WAVEFORMS
VDDQ
150 O utput
150
20pF
tORISE
tOFALL
1.7V VTH = 1.25V 0.7V
tPW H tPWL
2.5V Output Waveform
1ns
1ns
2.5V 1.7V VTH = 1.25V 0.7V 0V
LVTTL Input Test Waveform
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IDT5T9950/A 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
INDUSTRIAL TEMPERATURE RANGE
AC TIMING DIAGRAM
tREF tRPWH
REF
tRPW L
t()
FB
tODCV
tODCV
tCCJ H,
M, L Q
tSKEWPR tSKEW 0, 1
OTH ER Q
tSKEWPR tSKEW 0, 1
tSKEW2
INVER TE D Q
tSKEW2
tSKEW 3, 4 tSKEW 3, 4
REF D IVIDE D BY 2
tSKEW 3, 4
tSKEW1, 3, 4
tSKEW 2, 4
REF D IVIDE D BY 4
NOTES: PE: Skew: tSKEWPR: tSKEW0: tDEV: tODCV:
The AC Timing Diagram applies to PE=VDD. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align. The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated with 75 to VDDQ/2. The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. The skew between outputs when they are selected for 0tU. The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.) The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
tPWH is measured at 1.7V. tPWL is measured at 0.7V. tORISE and tOFALL are measured between 0.7V and 1.7V. tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
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IDT5T9950/A 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXX Device Type XX Package X Package
I
-40C to +85C (Industrial)
PF
Thin Quad Flat Pack
5T9950 5T9950A
2.5V Programmable Skew PLL Clock Driver TurboClock II Jr.
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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